With digital designs continuing to increase in density and complexity, it’s more difficult and critical than ever to fully understand the impact of design decisions on your Power Distribution Network’s (PDN) voltage and current performance.

Rather than treating PDN issues as a post-design afterthought in a physical prototype, you need a way to accurately identify and resolve every IR drop, current density issue, and voltage drop as part of your board layout process. The PDN Analyzer™ powered by CST® for Altium Designer® allows you – the PCB Designer – to easily resolve PDN issues as they arise in your board layout process, all right within the unified design workspace that you use every day.

In this webinar you will learn:

How to analyze your layouts regarding current density and voltage drops
Efficient use of this tool as part of the unified design process directly in your PCB editor
Optimization possibilities based on the results of this analysis
New and unique functionality of PDN 2.0